University Projects

This page contains details of all the projects I completed at my University, listed in chronological order.

I created this page primarily to declutter my CV. This page contains details of all the projects I completed at my University (in chronological order), whilst my resume contains all projects related to my professional career.

Wireless Sensor Network Modelling

🏒 Microsoft Innovation Lab
πŸ—“οΈ June 2019 – July 2019
πŸ“ Bengaluru, India
πŸ”— |
Simulator to optimize WSN architecture and end point hardware for cost-
space-lifetime. Full duplex ad hoc mesh WSN was deployed.

Automotive Security Suite

🏒 IIDC, Texas Instruments: Research and Development Project
πŸ—“οΈ August 2019 – October 2019
πŸ“ Bengaluru, India
Snoop resistant NFC for car security coupled with geofencing, real-time
tracking and low-cost retrofit solution with a connected car framework.

Flood Supply Bot

🏒 Ministry of Human Resource Development, Government of India
πŸ—“οΈ October 2019 – March 2020
πŸ“ IIT Bombay, Maharashtra
Optimized SatCom for food & medical aid over XBee networks. Triped
robot dispatching unit navigated by real-time OpenCV video processing.

Digital Audio Watermarking

🏒 FOSS Mini Project to aid DRM Enforcement
πŸ—“οΈ May 2020 – July 2020
πŸ“ PES University, Bengaluru
A FOSS methodology to aid DRM Enforcement of Digital Audio/any media
file streamed over OTT platforms, with a POC showcased using MATLAB.


🏒 Bestir into Technical Journalism and Reporting
πŸ—“οΈ August 2020 – Ongoing
πŸ“ Global Œ
Bestir into technical journalism via an independent platform for unbiased
and ethical technical reportingβ€”serving as an exercise in Web Development.

Memory Design and Testing

🏒 Design and Implementation of High Speed Ternary CAM Using Match Line Segmentation for IPv4 Router Prefix Matching
πŸ—“οΈ January 2021 – May 2021
πŸ“ PES University, Bengaluru
Implementation of longest prefix matching for ACLs in IPv4 routing table
lookup and packet identification for high-speed packet forwarding.

Capstone Project

🏒 Design and Implementation of Reversible Logic ALU on FPGA
πŸ—“οΈ February 2021 – December 2021
πŸ“PES University, Bengaluru
Scalable Reversible Logic Multiplier using SAK gate in the ALU, achieving -27% Gate
Count and -12.5% Quantum Cost. Leveraged by DNN for rapid MAC operations.